> ## Documentation Index > Fetch the complete documentation index at: https://docs.prescaler.ai/llms.txt > Use this file to discover all available pages before exploring further. # Verified hardware catalog > Per-chip build, QEMU, and hardware verification status for wizard catalog targets. [Vendor support](/vendors/support) covers what build adapters detect and drive. This page tracks how far each wizard catalog chip has been exercised in-house (compile, boot, debug), not merely that SVD data exists. Every catalog chip includes SVD register data for Peripheral Browser. Verification tiers describe runtime testing beyond that. ## Verification tiers **STM32F405RGTx**: in-house reference. Covered: bundled demo, QEMU, register browser, FreeRTOS task inspection over live debug. | Property | Value | | -------- | -------------------------- | | Core | Cortex-M4 | | Flash | 1024 KB | | RAM | 192 KB (128 + 64 CCM) | | Probes | ST-Link, J-Link, CMSIS-DAP | | QEMU | `netduino2` machine | | RTOS | FreeRTOS | QEMU's `netduino2` emulates Cortex-M3, not M4; a fidelity gap if you rely on QEMU to predict hardware behavior. CCM RAM uses a dedicated linker section: `__attribute__((section(".ccmram")))`. Compiles with the real toolchain and boots under QEMU (GDB confirms main loop execution). No in-house real-hardware pass. | Chip | Core | Flash | RAM | Probes | QEMU | | ------------- | --------- | ------ | ------ | -------------------------- | ------------------------------------------------------- | | STM32F411CEUx | Cortex-M4 | 512 KB | 128 KB | ST-Link, J-Link, CMSIS-DAP | `netduinoplus2` (F405/F407-class proxy, not exact F411) | No exact QEMU machine for F411; closest family model used. UART output not verified on QEMU. Not run on real F411 hardware. Compiles and links to a real ELF/bin/hex. Not booted under QEMU or on hardware in-house. | Chip | Core | Flash | RAM | Probes | RTOS | | ------------- | ---------- | ------- | ------- | -------------------------- | ----------- | | STM32F103C8Tx | Cortex-M3 | 64 KB | 20 KB | ST-Link, J-Link, CMSIS-DAP | FreeRTOS | | STM32H743ZITx | Cortex-M7 | 2048 KB | 1024 KB | ST-Link, J-Link, CMSIS-DAP | FreeRTOS | | nRF52840 | Cortex-M4 | 1024 KB | 256 KB | J-Link, CMSIS-DAP | FreeRTOS | | STM32F746ZGTx | Cortex-M7 | 1024 KB | 320 KB | ST-Link, J-Link, CMSIS-DAP | FreeRTOS | | STM32L476RGTx | Cortex-M4 | 1024 KB | 128 KB | ST-Link, J-Link, CMSIS-DAP | FreeRTOS | | STM32G031K8Tx | Cortex-M0+ | 64 KB | 8 KB | ST-Link, J-Link, CMSIS-DAP | Not offered | | ATSAMD21G18A | Cortex-M0+ | 256 KB | 32 KB | CMSIS-DAP, J-Link | Not offered | | nRF52832 | Cortex-M4 | 512 KB | 64 KB | J-Link, CMSIS-DAP | FreeRTOS | Per-chip notes: * **STM32F103C8Tx**: 20 KB RAM; tightest in catalog. QEMU attempt on `stm32vldiscovery` (F100 proxy) faulted early; cause not isolated. * **STM32H743ZITx**: No QEMU machine. Generated linker script uses single flash/RAM regions; dual-bank and D1/D2 domains need manual setup. * **nRF52840 / nRF52832**: ST-Link does not support Nordic. Use J-Link or CMSIS-DAP. * **STM32F746ZGTx**: Reuses F4-family peripheral map. Linker script models single RAM, not ITCM/DTCM split. * **STM32L476RGTx**: GPIO on AHB2; USART uses modern CR1/ISR/TDR layout. Linker script models single RAM, not SRAM1/SRAM2 split. * **STM32G031K8Tx**: 8 KB RAM; FreeRTOS not offered (same reasoning as tight AVR budgets). * **ATSAMD21G18A**: Different peripheral model (PM clock gating, grouped GPIO). GPIO/clock scope only in wizard; no UART path yet. SVD and catalog metadata present. Not compiled, booted, or run in-house. | Chip | Core | Flash | RAM | Probes | | -------------- | --------------- | ------- | ------ | -------------------------- | | STM32F407VGTx | Cortex-M4 | 1024 KB | 192 KB | ST-Link, J-Link, CMSIS-DAP | | STM32G071RBTx | Cortex-M0+ | 128 KB | 36 KB | ST-Link, J-Link, CMSIS-DAP | | RP2040 | Dual Cortex-M0+ | 2048 KB | 264 KB | CMSIS-DAP | | ESP32-WROOM-32 | Xtensa LX6 | 4096 KB | 520 KB | External JTAG | * **STM32F407VGTx**: Same OpenOCD family and SVD layout as F405; this exact part not individually tested. * **STM32G071RBTx**: Same G0 OpenOCD family as build-verified G031; this part not individually tested. * **RP2040**: Wizard generates single-core bring-up only. No core1, no RTOS option, no QEMU yet. * **ESP32-WROOM-32**: ESP-IDF adapter runs `idf.py build` when project is open. Flash uses native uploader path; external JTAG required (no built-in USB-JTAG on classic ESP32). Neither build nor flash verified on real hardware in-house. ## Getting started with a catalog target 1. Pick a target from the table above, or start with STM32F405 (reference platform). 2. Connect a supported probe, or run the STM32F405 demo in QEMU without hardware. 3. For CMake-supported targets, the wizard generates a buildable tree with linker script and register definitions. 4. Validate build, flash, and debug on your board before relying on catalog status for production work. ## Planned, not in catalog Research status only. These chips are not selectable in the wizard today. | Chip | Status | Detail | | ------------------------ | ----------- | -------------------------------------------------------------------------------------------- | | ESP32-S3 / ESP32-C3 | Not started | Need full ESP-IDF SDK (Xtensa for S3, RISC-V for C3); separate large install | | SAMD51 | Not started | SAMD21 in catalog; SAMD51 uses MCLK clock system; needs separate bring-up | | Teensy 4.x (i.MX RT1062) | Not started | No on-chip flash; boots from external QSPI via FlexSPI; needs bootloader-aware linker script | | ATmega328P | Not started | No CMSIS-SVD; debug needs debugWIRE hardware most Uno setups lack | ## Requesting a new target Open a GitHub issue with part number, SDK, probe, and what you need (build, flash, debug, or QEMU).